A Design of Rake Receiver for the High Speed Downlink Packet Access (HSDPA) system in 3G Mobile Networks

Abstract

This thesis addresses the problem of designing the receiver in high data rate systems. The case of multiple transmit antennas is also considered. Specific features of HSDPA system which are part of 3rd generation (3G) Wideband Code Division Multiple Access (WCDMA) evolution are exploited in channel estimation methods and in MIMO receiver design. Additionally, complexity reduction methods for Minimum Mean Square Error (MMSE) equalization are addressed. Based on the background knowledge on the HSDPA, this thesis will demonstrate the performance of HSDPA by simulating the system blocks using Matlab. The HSDPA is also implemented on the evaluation board LM3S2965 using ARM cortex M3 32-bit micro controller as a RAKE Receiver in the HSDPA system. This is a large topic about HSDPA system and it is divided into two main parts: transmitter and Rake receiver. In this thesis, I will focus on the Rake receiver, and my partner Mr.Phong will focus on the transmitter. In the course of research and working, we shared a number of documents as well as results of the transmitter as an input signal at the Rake receiver. We use the same hardware to test the theory.