FPGA implementation of viterbi decoder

Abstract

In this thesis, I present a basic field-programmable gate array implementation of convolutional encoder and Viterbi decoder with a code rate of ½. The data is inputted by computer using MATLAB and the decoded data is gotten by MATLAB into computer. Also the convolutional encoder, 2 bit soft decision, BPSK, AWGN channel and Viterbi decoder were implemented in MATLAB code. The BER was tested to evaluate the decoding performance. The main issue of this thesis is to find a method to implement the Viterbi decoder on hardware. With the testing results of simulation model, with minimizing the data path, register size and butterflies in the design, we try to achieve a low silicon cost design. The Viterbi decoder model includes the Branch Metric block, the AddCompare-Select block, the trace-back block, the decoding block and next state block. With all done, we further understand about the Viterbi decoding algorithm and the DSP implementation methods.