An Ensemble Convolution Neural Network For Wafer Detect Pattern Classification In Semiconductor Manufacturing

Abstract

Analysis of wafer maps is required for yield enhancement in semiconductor production since they contain important information obtained during manufacture about process, design, and test problem. Wafer maps provide data on multiple fault patterns on the wafer surface, and automated classification of these defects is crucial for discovering their causes. Moreover, the wafer maps data is collected in real-world semiconductor manufacturing, the majority class is a non-defect pattern with approximately 85% of total labeled data. As a result, the primary goal of this research is to determine the optimal classification model to maximize the classification result by applying the ensemble Convolutional neural network model through the WM-811K dataset. Also, the data augmentation techniques such as geometric transformation, and conditional generative adversarial networks (cGAN) were implemented to improve the performance of proposal model.